not to scale description the A3904 is a voice coil motor (vcm) driver, with an i 2 c-compatible serial interface. designed for camera autofocus and zoom applications, this high accuracy digital ic is provided in a wlcsp package ideal for portable devices. its operating voltage range is 2.4 to 5.5 v, and its maximum output current is 127 ma. output current is programmed via the i 2 c interface, in 500 ua increments, with clock rates up to 400 khz. i 2 c inputs set the internal d-to-a converter output voltage that is the reference for linear current control via a mosfet output sink transistor. to conserve battery power, a logic low signal on the sleepz input disables the output mosfet and reduces the supply current to <0.5 a. A3904 internal protection features include thermal shutdown and undervoltage lockout. logic input levels are independent of the supply voltage. the operating temperature range is ?40c to 85c. the A3904 is available in a bumped wafer level chip scale package (wlcsp) (suffix cg). 3904-ds, rev. 4 features and benefits ? fixed i 2 c logic thresholds ? 8-bit d-to-a converter ? 500 a resolution ? low voltage i 2 c serial interface ? low current-draw sleep mode ? 2.4 to 5.5 v operation ? 1.1 mm 0.7 mm, 0.5 mm maximum overall height wlcsp low voltage voice coil motor driver package: 6-ball wafer-level chip scale package (cg) functional block diagram A3904 1.1 mm 0.7 mm i 2 c serial interface iout vdd sda ew only scl gnd 8 bit dac bandgap ref 2.4 to 5.5 v sleepz i 2 c master i 2 c slave 1.8 k 1.8 k 2.4 1.8 v pad
low voltage voice coil motor driver A3904 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating units supply voltage v dd 6v logic input voltage range v in ?0.3 to v dd +0.3 v operating ambient temperature t a range e ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc selection guide part number packing package pb-free A3904ecgtr 4000 pieces per reel bumped wafer-level chip-scale package (wlcsp) pb-free chip with high-temperature solder balls (rohs compliant) terminal list number name description a1 sda i 2 c data input/output a2 scl i 2 c clock a3 vdd power supply b3 gnd ground b2 iout sink drive output b1 sleepz standby mode control a1 b1 a2 b2 a3 b3 orientation mark on bump side cg package pin-out diagram
low voltage voice coil motor driver A3904 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at t a = 25c, v dd = 2.4 to 5.5 v, unless otherwise noted characteristics symbol test conditions min. typ. max. units general supply current i dd ? 0.5 2 ma sleep mode (sleepz = low) ? <100 500 na uvlo enable threshold v uv(th) v dd rising ? 2.1 2.395 v uvlo hysteresis v uv(hys) 100 ? ? mv thermal shutdown temperature t jtsd temperature increasing ? 165 ? c thermal shutdown hysteresis .t jtsd(hys) t jtsd(hys) = t jtsd ? t j(recover) ?15?c power-up delay t d(on) ?10? s d-to-a converter resolution res target = 500 a / lsb ? 8 ? bit lsb relative accuracy inl code = 16 to 255, endpoint method ? 4 ? lsb lsb differential nonlinearity dnl guaranteed monotonic ? ? 1 lsb maximum output current i max code = 255 ? 127.5 ? ma gain error err a t j = 25c, code 16 to 255, v dd = 2.6 to 3.0 v ?10 <3 10 %fs gain error drift * ? err a t j = ?40c to 125c ? 0.2 ? lsb/c offset error i erros code = 1 0 1 5 ma code = 16 0.5 ? ? ma output output voltage range v out 0.500 ? v dd ?0.1 v output on resistance r ds(on) r sense + r sink , i out = 127.5 ma ? 3 ? i 2 c interface bus free time between stop and start t buf 1.3 ? ? s hold time start condition t hdsta 0.6 ? ? s setup time for repeated start condition t susta 0.6 ? ? s scl low time t low 1.3 ? ? s scl high time t high 0.6 ? ? s data setup time t sudat 100 ? ? ns data hold time t hddat 0 900 ns setup time for stop condition t susto 0.6 ? ? s logic input low level (sda, scl pins) v il ? ? 0.84 v logic input high level (sda, scl pins) v ih 1.26 ? ? v input hysteresis (sda, scl pins) v hys ? 100 ? mv sleepz input low level v inslp ? ? 0.7 v sleepz input high level v inslp 1.5 ? ? v logic input current i in v in = 0 v to v dd ?1 0 1 a output voltage (sda pin) v ol i load = 1.5 ma ? ? 0.36 v clock frequency (scl pin) f clk ? ? 400 khz output fall time (sda pin) t fo v ih to v il ? ? 250 ns *guaranteed by design and characterization, not production tested
low voltage voice coil motor driver A3904 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t susta t hdsta t sudat t hddat t buf t susto t high t low sda scl i 2 c interface timing diagram i 2 c control register bit definition bit name function 0 d0 dac lsb 1d1 2d2 3d3 4d4 5d5 6d6 7 d7 dac msb A3904 slave address bit definition bit operation 01234567 00011xx 1 read 0 write write register bit definition and timing diagram 1 2 3 4 5 6 7 8 9 k a k a 0 x x 1 1 0 0 0 d6 d5 d4 d3 d2 d1 d0 d7 control data address write t r a t s stop sda scl acknowledge (from A3904) acknowledge (from A3904)
low voltage voice coil motor driver A3904 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the A3904 output current is controlled by programming the d-to- a converter value via the i 2 c serial port. the target output current can be calculated by: i out = dac 500 a , where dac = 1 to 255. code = 0 is a disable state for the output sink drive. the dac will be set to code = 0 upon power-up or a fault condition on v dd . sleepz a logic low input disables all of the internal circuitry and prevents the ic from draining battery power. output range the voltage on the iout pin should be greater than 500 mv to guarantee the accuracy and linearity of the pro- grammed current. the output voltage is a function of the battery voltage, motor resistance, and the programmed load current. clamp diode when the output is turned off, the load induc- tance causes the output voltage to rise. a clamp diode, from iout to vdd, is integrated in the ic to ensure that the output voltage remains at a safe level. i 2 c interface this is a serial interface that uses two bus lines, scl and sda, to access the internal control registers. data is exchanged between a microcontroller (master) and the A3904 (slave). the clock input to scl is generated by the master, while the sda line functions as either an input or an open drain output, depending on the direction of the data. the i 2 c input thresholds do not depend on the v dd voltage of the A3904. the levels are fixed at approximately 1 v. the fixed levels allow the sda and scl lines to be pulled-up to a different logic level than the v dd supply of the 3904. timing considerations the control sequence of the com- munication through the i 2 c interface is composed of several steps in the following sequence: 1. start condition. defined by a negative edge on the sda line, while scl is high. 2. address cycle. 7 bits of address, plus 1 bit to indicate write (0) or read (1), and an acknowledge bit. the ad- dress setting is 0x18, 0x1a, 0x1c or 0x1e. 3. data cycles. write 8 bits of data that address the internal control register, followed by an acknowledge bit. 4. stop condition. defined by a positive edge on the sda line, while scl is high. except to indicate a start or stop condition, sda must be stable while the clock is high. sda can only be changed while scl is low. it is possible for the start or stop condition to occur at any time during a data transfer. the A3904 always responds by reset- ting the data transfer sequence. the read/write bit is set low to indicate a write cycle. multiple writes are allowed before issuing a stop condition. there are no readback functions incorporated into the A3904. the master monitors for an acknowledge pulse to determine if the slave device is responding to the address byte sent to the A3904. when the A3904 decodes the 7-bit address field as a valid address, it responds by pulling sda low during the ninth clock cycle. during a data write from the master, the A3904 pulls sda low during the clock cycle that follows the data byte, in order to indi- cate that the data has been successfully received. after sending either an address byte or a data byte, the master device must release the sda line before the ninth clock cycle, in order to allow this handshaking to occur. functional description
low voltage voice coil motor driver A3904 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com headroom the current may not reach the programmed level if there is not adequate headroom in the output circuit. the ic output voltage must be over 500 mv to guarantee normal linear operation. v dd , i load , and r load can be adjusted to ensure that the device operates in the linear range. if the equation shown below is not satisfied, the load current will be limited by the series impedance, and may not reach the programmed level v dd (min) ? r load (max) i out (max) 500 mv . i out errors relative accuracy (inl) this error is calculated by measuring the worse case deviation from a straight line, defined from end points. the straight line end points are defined by the actual mea- sured values at code = 16 and code = 255. see figure 1. differential nonlinearity (dnl) a measure of the monotonic- ity of the d-to-a converter. the slope of the line must always be positive for each incremental step, according to the following formula: dnl = ( i out( n +1) ? i out( n ) ) / lsb ? 1 (lsb) . where n is in the range 16 to 255. offset error the measured output current at input code = 16, compared to the ideal value according to the transfer function (8 ma). gain error the difference in the slopes of the ideal transfer function and the actual transfer function. the gain error is calcu- lated by subtracting out the offset error, at code = 16, from the actual transfer function. this calculated value is compared to the ideal transfer function and reported as a percentage of the ideal full scale value (127.5 ma). see figure 2. gain error drift the change in slope of the transfer function due to temperature, expressed as lsb/c. application information figure 1. relative accuracy error figure 2. gain error relative accuracy ( codes 16-255), errors exaggerated for clarity code code i out (ma) i out (ma) straight line between measured codes 16 and 255 actual dac, errors exaggerated for clarity calculated gain error, offset error removed 0 016 16 128 128 255 255 0 32.0 64.0 96.0 127.5 0 127.5 ideal dac offset error gain error inl
low voltage voice coil motor driver A3904 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com cg package, 6-bump wlcsp seating plane c 0.500 max 0.705 1.055 0.370 0.740 0.370 0.740 0.370 0.370 0.167 0.158 ? 0.170 c 0.05 6x a b b a 1 23 b a 1 23 1 23 a b c die orientation mark all dimensions nominal, not for tooling use dimensions in millimeters exact configuration at supplier discretion within limits shown a x ? 148 pcb layout reference view reference view of typical layout for solder pads all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b c terminal #a1 mark area copyright ?2007-2010, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com
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